AUIRS2336S【PDF 26/37 页】IC GATE DRIVER HV 3PHASE 28SOIC

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AUIRS2336S

Figure 25: Three phase inverter

DC+ BUS

Q1

ON

I U

V S1

Q2

D2

OFF

DC- BUS

Figure 26: Q1 conducting

Figure 27: D2 conducting

Also when the V phase current flows from the inductive load back to the inverter (see Figures 28 and 29), and Q4

IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V S2 ,

swings from the positive DC bus voltage to the negative DC bus voltage.

DC+ BUS

Q3

D3

OFF

I V

V S2

Q4

D4

OFF

DC- BUS

Figure 28: D3 conducting

Figure 29: Q4 conducting

However, in a real inverter circuit, the V S voltage swing does not stop at the level of the negative DC bus, rather it

swings below the level of the negative DC bus. This undershoot voltage is called “negative V S transient”.

The circuit shown in Figure 30 depicts one leg of the three phase inverter; Figures 31 and 32 show a simplified

illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from

the die bonding to the PCB tracks are lumped together in L C and L E for each IGBT. When the high-side switch is on,

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